1. Field of the Invention
The present invention is related to error detection and correction on computer system buses, and in particular, error correction code (ECC) support on the high-performance extension (PCI-X) to the peripheral component interconnect (PCI) computer system bus.
2. Description of the Related Art
All the major subsystems in a modem computer, including the CPU, the memory, and the storage subsystems have improved their fault tolerance. Today, however, PCI's ability to recover form parity exceptions is virtually non-existent. As PCI is at the core of the system architecture, its inability to recover from exceptions reduces the overall system availability. PCI is the weak link. If a parity error is detected on PCI, the system will crash.
As PCI performance increases, it is subject to the same error conditions. Failure rate increases as frequency increases and error rate increases as voltage swings decrease (e.g., as nominal operating voltage decreases). PCI needs further improvement to close the loop on end-to-end full error correction coverage. PCI-X is supposed to lead to follow-on technologies that include better channel protection. Therefore, for the above and other reasons it is imperative to improve error correction and detection on the PCI bus without adding cost to the system, as a better protection scheme may predicate the longevity of PCI-X.